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genlock adc KS0118C 1 introduction the KS0118C is a cmos integrated circuit designed for the genlock and nd conversion. it is a monolithic ic that enables an analog ntsc composite video signal to digitize at a clock rate that is synchronized and locked to the incoming video horizontal line frequency. it includes clamping function, 8-bit digitizing and creation of a line- locked sampling clock. it is possible to correspond to the video signal system of the ldp by using the ka9413, ka9414-d ics together, which is designed for the digital video signal processor. features ? ntsc video signal input ? line-locked sync and clock generation ? line-to-line jitter < 20 nsec ? differential gain 2% differential phase 2 ? programmable sample clock frequency from 25 to 30 mhz ? built-in 8-bit cmos analog to digital converter ? programmable gain control and automatic dc offset ? control for video signal input ? programmable pll time constants for tracking different input types ? correctly tracks line drop-outs ? provides a microprocessor 3-wire serial interface ? built-in decimation filter single power supply: + 5 v ordering information device package operating temperature KS0118C 80 - qfp - 1420c 120 to +75 c 80 - qfp - 1420c
KS0118C genlock adc 2 block diagram 70 48 55 35 39 40 clamp 8 bit adc phase det/ pll filter dto jitter reduction 4 5 crystal driver serial micom interface 19 25 27 sfrs sclk sdat xtl1 xtl2 vin sync detector digital offset control lpf pixel counter 16 output timing decimation filter cvbs<0:7> lock vs slice fsmp
genlock adc KS0118C 3 pin configuration ks0118 64 63 62 61 60 59 58 57 56 55 54 53 52 51 49 48 47 46 45 44 43 42 41 1 3 5 6 7 8 9 10 11 12 14 15 18 20 21 22 23 24 80 79 78 77 76 75 74 73 72 71 68 67 66 65 50 2 4 13 16 17 19 70 69 26 27 28 29 31 32 33 34 35 36 37 38 39 40 25 30 vrb vrt cref1 v dd (a) cagc vin gnd nc rref gnd v dd (a) rvco cref2 gnd nc nc rcpll rstb nc xtl1 xtl2 v dd (a) v dd (a) gnd nc nc syg frz fsmp ldp sfrs nc v dd gnd nc nc nc nc nc nc slice vs nc nc nc lock sdat nc sclk nc nc nc nc nc nc nc nc nc nc nc gnd v dd (a) gnd cvbs7 gnd v dd nc nc nc nc nc v dd v dd cvbs6 cvbs5 cvbs4 cvbs3 cvbs2 cvbs1 cvbs0
KS0118C genlock adc 4 pin description pin no symbol i/o description 1 rcpll i/o external filter pin for analog pll 2 rstb i system reset signal input (active low) 3 nc - no connection 4 xtl1 i pin 1 for external crystal oscillator 5 xtl2 o pin 2 for external crystal oscillator 6 v dd (a) - + 5 v supply voltage for analog domain 7 v dd (a) - + 5 v supply voltage for analog domain 8 gnd - ground 9 nc - no connection 10 nc - no connection 11 syg o line-locked horizontal sync signal 12 nc - no connection 13 frz i connect this pin to + 5 v for proper operation 14 vdd - + 5 v supply voltage for digital domain 15 gnd - ground 16 fsmp o freq. & phase compensated sample clock used for adc 17 ldp i connect this pin to + 5 v for proper operation 18 nc - no connection 19 sfrs i frame signal for serial data interface 20 nc - no connection 21 nc - no connection 22 nc - no connection 23 nc - no connection 24 nc - no connection 25 sclk i clock signal input for serial data interface 26 nc - no connection 27 sdat i/o serial data in serial interface 28 nc - no connection 29 nc - no connection 30 nc - no connection 31 nc - no connection
genlock adc KS0118C 5 32 nc - no connection 33 nc - no connection 34 nc - no connection 35 lock o high when the genlock is locked & in tracking state 36 nc - no connection 37 nc - no connection 38 nc - no connection 39 vs o vertical sync signal output 40 slice o sync level. low when cvbs < 32. this signal is not line locked 41 nc - no connection 42 nc - no connection 43 nc - no connection 44 nc - no connection 45 nc - no connection 46 v dd - +5 v supply voltage for digital domain 47 gnd - ground 48 cvbs0 o 8-bit composite video baseband signal 49 cvbs1 o 8-bit composite video baseband signal 50 cvbs2 o 8-bit composite video baseband signal 51 cvbs3 o 8-bit composite video baseband signal 52 cvbs4 o 8-bit composite video baseband signal 53 cvbs5 o 8-bit composite video baseband signal 54 cvbs6 o 8-bit composite video baseband signal 55 cvbs7 o 8-bit composite video baseband signal 56 gnd - ground 57 v dd - + 5 v supply voltage for digital domain 58 v dd - + 5 v supply voltage for digital domain 59 v dd (a) - + 5 v supply voltage for digital domain 60 gnd - ground 61 nc - no connection 62 nc - no connection pin description (continued) pin no symbol i/o description
KS0118C genlock adc 6 63 nc - no connection 64 nc - no connection 65 vrb i/o bottom voltage reference for adc 66 vrt i/o top voltage reference for adc 67 cref1 i/o decoupling pin for reference voltage 68 v dd (a) - +5 v supply voltage for analog domain 69 cagc i capacitor for offset control 70 vin i analog ntsc video signal input (1 vpp) 71 gnd - ground 72 nc - no connection 73 rref i/o current setting pin for internal analog circuitry 74 gnd - ground 75 v dd (a) - +5 v supply voltage for analog domain 76 rvco i/o current setting pin for analog vco 77 cref2 i/o decoupling pin for reference voltage 78 gnd - ground 79 nc - no connection 80 nc - no connection pin description (continued) pin no symbol i/o description
genlock adc KS0118C 7 absolute maximum ratings electrical characteristics (ta = 25 c, unless otherwise specified) characteristic symbol value unit supply voltage v dd - 0.5 ~ + 7.0 v voltage on any digital pin v pin gnd ~ v dd v operation temperature t opr - 20 ~ + 75 c storage temperature t stg - 55 ~ + 125 c characteristic symbol test conditions min. typ. max. unit digital input high voltage v ih v dd = 4.75 v 4.0 - - v digital input low voltage v il v dd = 5.25 v - - 1.0 v digital output high voltage v oh v dd = 4.75 v 4.0 - - v digital output low voltage v ol v dd = 5.25 v - - 1.0 ma static power current i ccs v dd = 5.25 v 34 74 94 ma dynamic power current i ccd v dd = 5.25 v 140 - 200 ma serial up i/o set - up time t us xtl = 24.576mhz - - 10 ns serial up i/o hold time t uh xtl = 24.576mhz - - 10 ns differential phase dp - - 2.0 - deg differential gain dg - - 2.0 - % signal to noise ratio snr - 35 - - db up maximum data rate f mpu v dd = 4.75v 5.0 - - mhz frequency lock range flt xtl = 24.576mhz 28.60 - 28.66 mhz
KS0118C genlock adc 8 test circuit ks0118 72 79 80 38 37 36 35 34 33 32 31 30 29 28 27 26 25 64 63 62 61 54 53 52 51 50 49 46 45 44 43 42 41 1 3 4 5 6 7 8 9 10 12 14 18 19 20 21 22 23 23 65 66 67 69 71 70 + 73 78 2 68 + 74 75 77 76 + + 13 17 + 15 + + 60 59 58 57 56 55 48 47 40 39 11 gnd 0.1 t 0.1 t 0.1 t 15 ? 10 t 2.4k 8k 0.1 t 3nf 1k 33pf 30k gnd 82 v11 120 200 v25 0.1 t v dd (a) 22 t 0.1 t 22 t v dd (a) 33pf 10k gnd v dd (a) v dd gnd 0.1uf 22uf 0.1uf 22uf v dd gnd x-tal 24.576mhz 0.1 t 22 t v dd gnd gnd 22 t 0.1 t v dd v dd (a) 0.1 ? 22 t v dd (a) rtsb fsmp 16 vin
genlock adc KS0118C 9 function description general description the KS0118C implements the funtions of an 8-bit adc, analog clamp, analog pll clock generator and digital timing generation. through the use of vlsl technology, the KS0118C combines analog circuits with digital signal processing to obtain locking characteristics not achievable by ordinary methods. the KS0118C uses one external frequency reference to create many different programmable line-lock sampling clocks. analog to digital converter the KS0118C uses a two step, 8-bit and auto zero adc to digitize the analog video input. the vrt and vrb pins are the top and bottom reference voltage for the adc. these references are generated internally but requires 0.1 m f decoupling capacitors to ground. external frequency reference the KS0118C requires an external stable frequency reference to generate the sampling clock. although a wide range of frequency will work with the genlock, it is recommended that 24.576 mhz be used as the reference. this can be derived from a standard crystal or an external clock. analog phase lock loop the KS0118C has an internal pll used for producing the sampling clock. this pll requires an external loop filter at pin 1 (rcpll) as shown in the application circuit. the ground connections for this filter should be placed close to pin 78, while the inputs should be located close to pin 1. the pll also requires an external resistor to convert the voltage of the rcpll node to a current for use by the internal vco. the voltage of pin 76 (rvco) will track rcpll, although the absolute voltage of these pins depends on many factors, it will be between 0.75 and 4.50v. the voltage will exhibit the standard characteristics of an analog pll.
KS0118C genlock adc 10 figure 1. data path propagation delay and key timing signals figure 2. digitized code levels t dsvs t dslice t dd t dsys adc code = 32 vin fsmp cvbs slice vs 100 ire 40 ire white level code = 224.234 160 (170) codes blank level code = 84
genlock adc KS0118C 11 application circuit ks0118 72 79 80 38 37 36 35 34 33 32 31 30 29 28 27 26 25 64 63 62 61 54 53 52 51 50 49 46 45 44 43 42 41 1 3 4 5 6 7 8 9 10 12 14 18 19 20 21 22 23 23 65 66 67 69 71 70 + 73 78 2 68 + 74 75 77 76 + + 13 17 + ks9411 15 16 ks9411 + ks9411 + 60 59 58 57 56 55 48 47 40 39 11 gnd 0.1 t 0.1 t 0.1 t 15 ? 10 t 2.4k 8k 0.1 t 3nf 1k 33pf 30k gnd 82 v11 120 200 v25 0.1 t v dd (a) 22 t 0.1 t 22 t v dd (a) 33pf 10k gnd v dd (a) v dd gnd 0.1uf 22uf 0.1uf 22uf v dd gnd x-tal 24.576mhz 0.1 t 22 t v dd gnd gnd 22 t 0.1 t v dd v dd (a) 0.1 ? 22 t v dd (a) composit video signal input ( 1vpp ) from ka9411 0.1 m f

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